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Disambiguation of "Kim, Kyung Whan"

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A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 380-382. IEEE, (2019)

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Robin Kimmel University of Stuttgart

Seongkyeong Kim University of Stuttgart

Kim Müller University of Stuttgart

Kim Glumann University of Stuttgart

Kim Meliani University of Stuttgart

 

Other publications of authors with the same name

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 380-382. IEEE, (2019)18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface., , , , , , , , , and 12 other author(s). ISSCC, page 318-319. IEEE, (2016)A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits., , , , , , , , and . J. Solid-State Circuits, 50 (1): 191-203 (2015)Group Dancing Mobile Flower Robots with Moving Mechanism, Mobility and Localization Functions., , , , and . ISR/ROBOTIK, page 1-6. VDE Verlag, (2010)A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces., , , , , , , , , and 9 other author(s). J. Solid-State Circuits, 47 (6): 1436-1447 (2012)Design considerations of HBM stacked DRAM and the memory architecture extension., , , , , , and . CICC, page 1-8. IEEE, (2015)A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface., , , , , , , , , and 6 other author(s). ISCAS, page 3861-3864. IEEE, (2010)An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM., , , , , , , , , and 1 other author(s). VLSIC, page 1-2. IEEE, (2014)