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A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.

H. Lee, H. Choi, B. Shin, K. Kim, K. Kim, J. Kim, K. Kim, J. Jung, J. Kim, E. Park, J. Kim, J. Kim, J. Cho, N. Rye, J. Chun, Y. Kim, C. Kim, Y. Choi, and B. Chung. J. Solid-State Circuits, 47 (6): 1436-1447 (2012)

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A Stochastic Evolution Algorithm for the Graph Covering Problem and Its Application to the Technology Mapping.D. Lee, H. Choi, L. Park, C. Park, and S. Hwang. International Conference on Evolutionary Computation, page 475-479. (1996)Access network service delivery using nested workflow process.H. Kim, B. Chung, H. Choi, and S. Kim. NOMS (2), page 205-217. IEEE, (2004)Virtual Simulation Mechanism for Distributed Energy Resources Based on Home Energy System Facilities.T. Ku, W. Park, and H. Choi. ICCE, page 1-2. IEEE, (2019)Development of a Multiuser Interaction Middleware based on D2D communications.Y. Yun, and H. Choi. ICOIN, page 480-485. IEEE, (2017)Autonomic system management for personal digital assistants.Y. You, H. Choi, and D. Han. IEEE Trans. Consumer Electronics, 54 (2): 940-946 (2008)7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.T. Tanaka, M. Helm, T. Vali, R. Ghodsi, K. Kawai, J. Park, S. Yamada, F. Pan, Y. Einaga, A. Ghalam and 51 other author(s). ISSCC, page 142-144. IEEE, (2016)Approximate Performance Models of Polling Systems Using Stochastic Petri Nets.H. Choi, and K. Trivedi. INFOCOM, page 2306-2314. IEEE Computer Society, (1992)Energy information collecting agent for IoT big data system.T. Ku, W. Park, and H. Choi. ICTC, page 1134-1136. IEEE, (2017)A C-Based RTL Design Verification Methodology for Complex Microprocessor.J. Yim, Y. Hwang, C. Park, H. Choi, W. Yang, H. Oh, I. Park, and C. Kyung. DAC, page 83-88. ACM Press, (1997)A load balancing scheme using a chord algorithm for DDSB service.G. Yoon, H. Choi, and W. Kim. BigComp, page 291-295. IEEE Computer Society, (2014)

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A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.

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A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.