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Disambiguation of "Lee, Dong-Uk"

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A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.

, , , , , , , , , , , , , , , , , , , , , , , , and . J. Solid-State Circuits, 55 (1): 167-177 (2020)

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Moosung Lee University of Stuttgart

Dongwon Lee University of Stuttgart

Junghwa Lee University of Stuttgart

Laura-Ann Dönges University of Stuttgart

Yoonhee Lee University of Stuttgart

 

Other publications of authors with the same name

Electrical Characterization of Nano-Floating Gated Silicon-on-Insulator Memory with In2O3 Nano-Particles Embedded in Polyimide Insulator., , , , , , and . IEICE Transactions, 91-C (5): 747-750 (2008)A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology., , , , , , , , , and 12 other author(s). ISSCC, page 282-283. IEEE, (2008)A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits., , , , , , , , and . J. Solid-State Circuits, 50 (1): 191-203 (2015)A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS., , , , , , , , , and 14 other author(s). ISSCC, page 140-141. IEEE, (2009)An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM., , , , , , , , , and 1 other author(s). VLSIC, page 1-2. IEEE, (2014)Design considerations of HBM stacked DRAM and the memory architecture extension., , , , , , and . CICC, page 1-8. IEEE, (2015)Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface., , , , , , , , , and 3 other author(s). ISSCC, page 280-281. IEEE, (2008)Robust Frame Synchronization for Low Signal-to-Noise Ratio Channels Using Energy-Corrected Differential Correlation., , and . EURASIP J. Wireless Comm. and Networking, (2009)A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 380-382. IEEE, (2019)A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx., , , , , , , , , and 15 other author(s). J. Solid-State Circuits, 55 (1): 167-177 (2020)