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Disambiguation of "Batterywala, Shabbir H."

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Efficient Analog/RF Layout Closure with Compaction Based Legalization.

, , and . VLSI Design, page 137-142. IEEE Computer Society, (2009)

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H. Binz

H. Bungartz

H. Binz

H. Binz

H. J. Dennig

 

Other publications of authors with the same name

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects., , , , , and . VLSI Design, page 875-880. IEEE Computer Society, (2007)2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids., , , and . VLSI Design, page 186-191. IEEE Computer Society, (2015)A Method to Estimate Slew and Delay in Coupled Digital Circuits., and . VLSI Design, page 411-416. IEEE Computer Society, (2003)On Efficient and Robust Constraint Generation for Practical Layout Legalization., , , , and . ISQED, page 379-384. IEEE Computer Society, (2008)Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports., and . VLSI Design, page 500-. IEEE Computer Society, (2001)A 3-dimensional FEM Based Resistance Extraction., and . VLSI Design, page 565-570. IEEE Computer Society, (2007)Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables., and . VLSI Design, page 989-994. IEEE Computer Society, (2004)Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks., and . VLSI Design, page 169-174. IEEE Computer Society, (1999)Cell Swapping Based Migration Methodology for Analog and Custom Layouts., , , , and . ISQED, page 450-455. IEEE Computer Society, (2008)A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills., , , and . VLSI Design, page 129-134. IEEE Computer Society, (2006)