%0 Conference Paper %1 conf/vlsid/BatterywalaS04 %A Batterywala, Shabbir H. %A Shenoy, Narendra V. %B VLSI Design %D 2004 %I IEEE Computer Society %K dblp %P 989-994 %T Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2004.html#BatterywalaS04 %@ 0-7695-2072-3

@inproceedings{conf/vlsid/BatterywalaS04, added-at = {2017-05-23T00:00:00.000+0200}, author = {Batterywala, Shabbir H. and Shenoy, Narendra V.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2e3363e2e78e29d511112c6829d1e5553/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2004}, ee = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261059}, interhash = {30d55cd18d7b5b482b95548ead07df8e}, intrahash = {e3363e2e78e29d511112c6829d1e5553}, isbn = {0-7695-2072-3}, keywords = {dblp}, pages = {989-994}, publisher = {IEEE Computer Society}, timestamp = {2019-09-27T18:12:05.000+0200}, title = {Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2004.html#BatterywalaS04}, year = 2004 }