%0 Conference Paper %1 conf/vlsid/RajagopalanBB09 %A Rajagopalan, Subramanian %A Bhattacharya, Sambuddha %A Batterywala, Shabbir H. %B VLSI Design %D 2009 %I IEEE Computer Society %K dblp %P 137-142 %T Efficient Analog/RF Layout Closure with Compaction Based Legalization. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2009.html#RajagopalanBB09 %@ 978-0-7695-3506-7

@inproceedings{conf/vlsid/RajagopalanBB09, added-at = {2015-04-20T00:00:00.000+0200}, author = {Rajagopalan, Subramanian and Bhattacharya, Sambuddha and Batterywala, Shabbir H.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2393be4a39d8e36d84ee8c1d912004701/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2009}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2009.61}, interhash = {d2ad43bbaaec6f921e6830fad48f712d}, intrahash = {393be4a39d8e36d84ee8c1d912004701}, isbn = {978-0-7695-3506-7}, keywords = {dblp}, pages = {137-142}, publisher = {IEEE Computer Society}, timestamp = {2016-02-02T11:08:26.000+0100}, title = {Efficient Analog/RF Layout Closure with Compaction Based Legalization.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2009.html#RajagopalanBB09}, year = 2009 }