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At-speed Test of High-Speed DUT Using Built-Off Test Interface., , , , , , , and . Asian Test Symposium, page 269-274. IEEE Computer Society, (2010)Power-aware multi-voltage custom memory models for enhancing RTL and low power verification., , and . ICCD, page 24-31. IEEE Computer Society, (2015)Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level., , and . J. Low Power Electronics, 5 (3): 339-353 (2009)Test Generation for Microprocessors., and . IEEE Trans. Computers, 29 (6): 429-441 (1980)Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays., and . IEEE Trans. Computers, 39 (4): 426-435 (1990)Abstraction Techniques for Validation Coverage Analysis and Test Generation., , and . IEEE Trans. Computers, 47 (1): 2-14 (1998)Efficient Algorithms for Testing Semiconductor Random-Access Memories., , and . IEEE Trans. Computers, 27 (6): 572-576 (1978)The Testability of Generalized Counters Under Multiple Faulty Cells., and . IEEE Trans. Computers, 39 (11): 1378-1385 (1990)CEDA: Control-Flow Error Detection Using Assertions., and . IEEE Trans. Computers, 60 (9): 1233-1245 (2011)A Unified Framework for Design Validation and Manufacturing Test., , and . ITC, page 875-884. IEEE Computer Society, (1996)