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Floating-Point Matrix Multiplication in a Polymorphic Processor., and . FPT, page 249-252. IEEE, (2007)Multithreading on reconfigurable hardware: An architectural approach., and . Microprocessors and Microsystems - Embedded Hardware Design, 36 (8): 695-704 (2012)Cost-Efficient SHA Hardware Accelerators., , , and . IEEE Trans. VLSI Syst., 16 (8): 999-1008 (2008)Hardwired MPEG-4 repetitive padding., , and . IEEE Trans. Multimedia, 7 (2): 261-268 (2005)Memory Organization with Multi-Pattern Parallel Accesses., , and . DATE, page 1420-1425. ACM, (2008)Arbitrating Instructions in an pmu-Coded CCM., and . FPL, volume 2778 of Lecture Notes in Computer Science, page 81-90. Springer, (2003)On implementability of Polymorphic Register Files., , and . ReCoSoC, page 1-6. IEEE, (2012)HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation., , , , , , , , and . FPL, page 402-408. IEEE, (2007)Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling., , , and . IPDPS, IEEE, (2006)Scalability Evaluation of a Polymorphic Register File: A CG Case Study., , , , and . ARCS, volume 6566 of Lecture Notes in Computer Science, page 13-25. Springer, (2011)