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Disambiguation of "Uhrig, Sascha"

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Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling.

, , , and . IPDPS, IEEE, (2006)

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Sascha Kolatschek University of Stuttgart

Sascha Polatkan University of Stuttgart

Sascha Ritschel University of Stuttgart

Marvin Sascha Wahl University of Stuttgart

 

Other publications of authors with the same name

Case study: Performance and WCET analysis for parallelised avionic applications with ODC2., , , , , and . INDIN, page 1400-1407. IEEE, (2015)Risks and chances of many-core processors.. HPCS, page 80. IEEE, (2009)Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore., , , , , , , , , and 22 other author(s). ACM Trans. Embedded Comput. Syst., 15 (3): 53 (2016)Energy Management for Embedded Multithreaded Processors with Integrated EDF Scheduling., and . ARCS, volume 3432 of Lecture Notes in Computer Science, page 1-17. Springer, (2005)Closed Loop Controller for Multicore Real-Time Systems., and . ARCS, volume 10793 of Lecture Notes in Computer Science, page 45-56. Springer, (2018)Static Speculation as Post-link Optimization for the Grid Alu Processor., , , and . Euro-Par Workshops, volume 6586 of Lecture Notes in Computer Science, page 145-152. Springer, (2010)A Two-Layered Management Architecture for Building Adaptive Real-Time Systems., , , and . SEUS, volume 5287 of Lecture Notes in Computer Science, page 126-137. Springer, (2008)IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor., , , and . HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 125-139. Springer, (2009)jamuth: an IP processor core for embedded Java real-time systems., and . JTRES, page 230-237. ACM, (2007)CARUSO - Project Goals and Principal Approach., , , , , and . GI Jahrestagung (2), volume P-51 of LNI, page 616-620. GI, (2004)