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Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore., , , , , , , , , and 22 other author(s). ACM Trans. Embedded Comput. Syst., 15 (3): 53 (2016)WCTT bounds for MPI primitives in the PaterNoster NoC., , , and . SIGBED Review, 13 (4): 25-30 (2016)A Two-Layered Management Architecture for Building Adaptive Real-Time Systems., , , and . SEUS, volume 5287 of Lecture Notes in Computer Science, page 126-137. Springer, (2008)IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor., , , and . HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 125-139. Springer, (2009)An IP Core for Embedded Java Systems., , and . SAMOS, volume 4599 of Lecture Notes in Computer Science, page 263-272. Springer, (2007)Analysing Real-Time Behaviour of Collective Communication Patterns in MPI., , , and . RTNS, page 137-147. ACM, (2018)Predictable dynamic instruction scratchpad for simultaneous multithreaded processors., , , and . MEDEA@PACT, page 38-45. ACM, (2008)Using SMT to Hide Context Switch Times of Large Real-Time Tasksets., , , and . RTCSA, page 255-264. IEEE Computer Society, (2010)Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability., , , , , , , , , and 7 other author(s). IEEE Micro, 30 (5): 66-75 (2010)A hard real-time capable multi-core SMT processor., , , , , , , and . ACM Trans. Embedded Comput. Syst., 12 (3): 79:1-79:26 (2013)