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FPGA acceleration of the pair-HMMs forward algorithm for DNA sequence analysis., , and . BIBM, page 1465-1470. IEEE Computer Society, (2015)Compiler assisted runtime task scheduling on a reconfigurable computer., , and . FPL, page 44-50. IEEE, (2009)Quipu: A Statistical Model for Predicting Hardware Resources., , , , , and . TRETS, 6 (1): 3:1-3:25 (2013)High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain., , , , and . EUC, page 138-145. IEEE Computer Society, (2014)Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures., , , , , and . DATE, page 1379-1384. IEEE, (2012)Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms., , , , and . FCCM, page 28. IEEE Computer Society, (2016)FPGA-accelerated Monte-Carlo integration using stratified sampling and Brownian bridges., , , and . FPT, page 68-75. IEEE, (2014)Run-time optimization of a dynamically reconfigurable embedded system through performance prediction., , , , , , and . FPL, page 1-8. IEEE, (2013)Area constraint propagation in high level synthesis., , and . FPT, page 247-252. IEEE, (2012)An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm., , , and . SAMOS, page 221-227. IEEE, (2015)