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Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath.

, and . IEEE Trans. VLSI Syst., 17 (9): 1348-1352 (2009)

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Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath., and . IEEE Trans. VLSI Syst., 17 (9): 1348-1352 (2009)A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters., , and . IEEE Trans. VLSI Syst., 19 (10): 1733-1745 (2011)Contention resolution algorithm for common subexpression elimination in digital filter design., , and . IEEE Trans. on Circuits and Systems, 52-II (10): 695-700 (2005)A fast and compact circuit for integer square root computation based on Mitchell logarithmic method., , , , and . ISCAS, page 1235-1238. IEEE, (2012)Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (10): 1898-1907 (2007)Matrix Inversion on Reconfigurable Hardware using Binary-coded z-path CORDIC., and . APCCAS, page 1176-1179. IEEE, (2006)Efficient algorithms for common subexpression elimination in digital filter design., , and . ICASSP (5), page 137-140. IEEE, (2004)Time-multiplexed Data Flow Graph for the Design of Configurable Multiplier Block., , and . ISCAS, page 1145-1148. IEEE, (2009)A novel counter-based low complexity inner-product architecture for high speed inputs., , , and . ISCAS, page 705-708. IEEE, (2010)A High-Throughput VLSI Architecture for Real-Time Full-HD Gradient Guided Image Filter., and . IEEE Trans. Circuits Syst. Video Techn., 29 (6): 1868-1877 (2019)