Author of the publication

A novel counter-based low complexity inner-product architecture for high speed inputs.

, , , and . ISCAS, page 705-708. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture., , and . IEEE Trans. on Circuits and Systems, 59-I (12): 2945-2955 (2012)Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction., , and . IEEE Trans. Computers, 64 (12): 3417-3429 (2015)Fuzzy-ART based adaptive digital watermarking scheme., , and . IEEE Trans. Circuits Syst. Video Techn., 15 (1): 65-81 (2005)A signed integer programmable power-of-two scaler for 2n-1, 2n, 2n+1 RNS., , and . ISCAS, page 2211-2214. IEEE, (2013)Efficient structural adder pipelining in transposed form FIR filters., , , and . DSP, page 311-314. IEEE, (2015)A Generalized Time-Frequency Subtraction Method for Robust Speech Enhancement Based on Wavelet Filter Banks Modeling of Human Auditory System., and . IEEE Trans. Systems, Man, and Cybernetics, Part B, 37 (4): 877-889 (2007)Watermarking for IP Protection through Template Substitution at Logic Synthesis Level., and . ISCAS, page 3687-3690. IEEE, (2007)Design of programmable FIR filters using Canonical Double Based Number Representation., and . ISCAS, page 1183-1186. IEEE, (2014)Fast hard multiple generators for radix-8 Booth encoded modulo 2n-1 and modulo 2n+1 multipliers., and . ISCAS, page 717-720. IEEE, (2010)Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response., , and . IEEE Trans. Information Forensics and Security, 14 (4): 1109-1123 (2019)