Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

TSV stress aware timing analysis with applications to 3D-IC layout optimization.

J. Yang, K. Athikulwongse, Y. Lee, S. Lim, and D. Pan. DAC, page 803-806. ACM, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jaekeun Lim University of Stuttgart

Other publications of authors with the same name

Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs.T. Song, and S. Lim. J. Inform. and Commun. Convergence Engineering, (2015)Backend Dielectric Reliability Full Chip Simulator.M. Bashir, C. Chen, L. Milor, D. Kim, and S. Lim. IEEE Trans. VLSI Syst., 22 (8): 1750-1762 (2014)Distributed TSV Topology for 3-D Power-Supply Networks.M. Healy, and S. Lim. IEEE Trans. VLSI Syst., 20 (11): 2066-2079 (2012)Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing.I. Baskaya, D. Anderson, and S. Lim. IEEE Trans. on Circuits and Systems, 56-II (7): 565-569 (2009)Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations.M. Jung, D. Pan, and S. Lim. IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (11): 1694-1707 (2013)Stacking integration methodologies in 3D IC for 3D ultrasound image processing application: A stochastic flash ADC design case study.H. Attarzadeh, S. Lim, and T. Ytterdal. ISCAS, page 1266-1269. IEEE, (2015)How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.M. Jung, T. Song, Y. Wan, Y. Lee, D. Mohapatra, H. Wang, G. Taylor, D. Jariwala, V. Pitchumani, P. Morrow and 3 other author(s). CICC, page 1-4. IEEE, (2013)Block-level 3D IC design with through-silicon-via planning.D. Kim, R. Topaloglu, and S. Lim. ASP-DAC, page 335-340. IEEE, (2012)Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects.Y. Lee, and S. Lim. ISQED, page 228-335. IEEE, (2012)Physical Planning with Retiming.J. Cong, and S. Lim. ICCAD, page 2-7. IEEE Computer Society, (2000)

PUMA

Disambiguation of "Lim, Sung Kyu"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

TSV stress aware timing analysis with applications to 3D-IC layout optimization.

Please choose a person to relate this publication to

Jaekeun Lim University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Lim, Sung Kyu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML TSV stress aware timing analysis with applications to 3D-IC layout optimization.

Please choose a person to relate this publication to

Jaekeun Lim University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

TSV stress aware timing analysis with applications to 3D-IC layout optimization.