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Disambiguation of "Berthold, Jörg"

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The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.

, , , and . ISLPED, page 237-242. IEEE, (1996)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dr. phil. Christian Jörg University of Stuttgart

Fabian Jörg University of Stuttgart

Jörg Desel

Das ist Informatik (Eds.) Springer, (2001)

Jörg Förstner University of Stuttgart

Jörg Roth University of Stuttgart

 

Other publications of authors with the same name

Low power design of the X-GOLD® SDR 20 baseband processor., , , , , , , and . DATE, page 792-793. IEEE, (2010)In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations., , , , and . J. Solid-State Circuits, 42 (7): 1583-1592 (2007)Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 392-401. Springer, (2004)Architecture and implementation of a Software-Defined Radio baseband processor., , , , , , , , , and 8 other author(s). ISCAS, page 2193-2196. IEEE, (2011)The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits., , , and . IEEE Trans. VLSI Syst., 5 (4): 360-368 (1997)Degradation and recovery of variability due to BTI., , , , , and . Microelectronics Reliability, (2016)A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions., , , , , , , , , and 9 other author(s). J. Solid-State Circuits, 42 (1): 134-144 (2007)Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies., , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 41-50. Springer, (2003)Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 789-798. Springer, (2004)Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes., , , , , and . VLSI-SoC (Selected Papers), volume 200 of IFIP, page 229-245. Springer, (2003)