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Guest Editorial Special Section on Hardware Security and Trust.

, , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (6): 873-874 (2015)

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SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states., , , and . ITC, page 1-8. IEEE Computer Society, (2013)Secure hardware-entangled field programmable gate arrays., , , , and . J. Parallel Distrib. Comput., (2019)Deeply hardware-entangled reconfigurable logic and interconnect., , , and . ReConFig, page 1-8. IEEE, (2015)Statistical Learning in Chip (SLIC)., , , , , , , and . ICCAD, page 664-669. IEEE, (2015)A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes., , , , and . ICCD, page 523-528. IEEE Computer Society, (2009)An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS., , , and . ESSCIRC, page 65-68. IEEE, (2019)Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines., , , , , and . CICC, page 415-418. IEEE, (2008)Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime., , , , , , and . ICCD, page 94-101. IEEE Computer Society, (2012)An efficient reliable PUF-based cryptographic key generator in 65nm CMOS., and . DATE, page 1-6. European Design and Automation Association, (2014)Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers., , and . HOST, page 7-13. IEEE Computer Society, (2015)