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Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers.

, , and . HOST, page 7-13. IEEE Computer Society, (2015)

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Univ. -Prof. Dr. -Ing. Thomas Maier University of Stuttgart

Entwicklung eines aktiven Aufgabenwarn- und assistenzsystems für Unterarm und Handgelenk im Kontext von chirurgischen Armassistenzsystemen und Exoskeletten, , and . Stuttgarter Symposium für Produktentwicklung SSP 2023 : Tagungsband zur Konferenz, Stuttgart, 25. Mai 2023, page 536-545. Stuttgart, Fraunhofer IAO, (2023)
Entwicklung eines aktiven Aufgabenwarn- und assistenzsystems für Unterarm und Handgelenk im Kontext von chirurgischen Armassistenzsystemen und Exoskeletten, , and . Stuttgarter Symposium für Produktentwicklung SSP 2023 : Tagungsband zur Konferenz, Stuttgart, 25. Mai 2023, page 536-545. Stuttgart, Fraunhofer IAO, (2023)Anpassbare Mensch-Maschine-Schnittstellen zwischen Adaptivität und Individualisierung, , , , and . Stuttgarter Symposium für Produktentwicklung SSP 2023 : Tagungsband zur Konferenz, Stuttgart, 25. Mai 2023, page 524-535. Stuttgart, Fraunhofer IAO, (2023)Experiment on digital anthropometric measurements of the hand using machine vision, , and . Stuttgarter Symposium für Produktentwicklung SSP 2023 : Tagungsband zur Konferenz, Stuttgart, 25. Mai 2023, page 428-439. Stuttgart, Fraunhofer IAO, (2023)
 

Other publications of authors with the same name

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states., , , and . ITC, page 1-8. IEEE Computer Society, (2013)Deeply hardware-entangled reconfigurable logic and interconnect., , , and . ReConFig, page 1-8. IEEE, (2015)Secure hardware-entangled field programmable gate arrays., , , , and . J. Parallel Distrib. Comput., (2019)Statistical Learning in Chip (SLIC)., , , , , , , and . ICCAD, page 664-669. IEEE, (2015)A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes., , , , and . ICCD, page 523-528. IEEE Computer Society, (2009)An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS., , , and . ESSCIRC, page 65-68. IEEE, (2019)Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines., , , , , and . CICC, page 415-418. IEEE, (2008)An efficient reliable PUF-based cryptographic key generator in 65nm CMOS., and . DATE, page 1-6. European Design and Automation Association, (2014)Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime., , , , , , and . ICCD, page 94-101. IEEE Computer Society, (2012)Data retention in MLC NAND flash memory: Characterization, optimization, and recovery., , , , and . HPCA, page 551-563. IEEE Computer Society, (2015)