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Guest Editorial Special Section on Hardware Security and Trust.

, , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (6): 873-874 (2015)

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Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits., , and . J. Low Power Electronics, 7 (4): 573-584 (2011)Efficient Construction of Aliasing-Free Compaction Circuitry., and . IEEE Micro, 22 (5): 82-92 (2002)Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation., and . DFT, page 325-333. IEEE Computer Society, (2002)Regaining Trust in VLSI Design: Design-for-Trust Techniques., , and . Proceedings of the IEEE, 102 (8): 1266-1282 (2014)Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing.. Asian Test Symposium, page 78-83. IEEE Computer Society, (2011)Toggle-Based Masking Scheme for Clustered Unknown Response Bits.. European Test Symposium, page 105-110. IEEE Computer Society, (2011)Test-mode-only scan attack using the boundary scan chain., , and . ETS, page 1-6. IEEE, (2014)Scan Power Reduction Through Test Data Transition Frequency Analysis., , and . ITC, page 844-850. IEEE Computer Society, (2002)Aggressive Test Power Reduction Through Test Stimuli Transformation., and . ICCD, page 542-547. IEEE Computer Society, (2003)On Improving the Security of Logic Locking., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (9): 1411-1424 (2016)