PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Bhunia, Swarup"

Author of the publication

copydeleteadd this publication to your clipboard
Guest Editorial Special Section on Hardware Security and Trust.

, , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (6): 873-874 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Bhunia, Swarup
add a person with the name Bhunia, Swarup
 

Other publications of authors with the same name

MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications., , , , and . IEEE Trans. VLSI Syst., 23 (6): 1005-1016 (2015)Security Through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP., and . HOST, page 96-99. IEEE Computer Society, (2009)A Flexible Architecture for Systematic Implementation of SoC Security Policies., , and . ICCAD, page 536-543. IEEE, (2015)Sequential hardware Trojan: Side-channel aware design and placement., , , , and . ICCD, page 297-300. IEEE Computer Society, (2011)Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar., and . ISQED, page 697-701. IEEE Computer Society, (2008)Secure and Trusted SoC: Challenges and Emerging Solutions., , and . MTV, page 29-34. IEEE Computer Society, (2013)Current based PUF exploiting random variations in SRAM cells., , , and . DATE, page 277-280. IEEE, (2016)Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis., , , , and . IEEE Trans. VLSI Syst., 14 (9): 1034-1039 (2006)Self-Healing Design in Deep Scaled CMOS Technologies., , , , and . Journal of Circuits, Systems, and Computers, (2012)Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations., , , and . IEEE Trans. VLSI Syst., 13 (11): 1286-1295 (2005)