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Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.

R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. FPT, page 58-65. IEEE, (2013)

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Davide Padeletti University of Stuttgart

PD Dr. rer. nat. Davide Cesare Veniani University of Stuttgart

Other publications of authors with the same name

Breadth First Search on APEnet+.M. Bernaschi, M. Bisson, E. Mastrostefano, and D. Rossetti. SC Companion, page 248-253. IEEE Computer Society, (2012)UCX: An Open Source Framework for HPC Network APIs and Beyond.P. Shamis, M. Venkata, M. Lopez, M. Baker, O. Hernandez, Y. Itigin, M. Dubman, G. Shainer, R. Graham, L. Liss and 10 other author(s). Hot Interconnects, page 40-43. IEEE Computer Society, (2015)GPU peer-to-peer techniques applied to a cluster interconnect.R. Ammendola, M. Bernaschi, A. Biagioni, M. Bisson, M. Fatica, O. Frezza, F. Cicero, A. Lonardo, E. Mastrostefano, P. Paolucci and 4 other author(s). CoRR, (2013)NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features.A. Lonardo, F. Ameli, R. Ammendola, A. Biagioni, O. Frezza, G. Lamanna, F. Cicero, M. Martinelli, P. Paolucci, E. Pastorelli and 7 other author(s). CoRR, (2014)Exploring OpenSHMEM Model to Program GPU-based Extreme-Scale Systems.S. Potluri, D. Rossetti, D. Becker, D. Poole, M. Venkata, O. Hernandez, P. Shamis, M. Lopez, M. Baker, and W. Poole. OpenSHMEM, volume 9397 of Lecture Notes in Computer Science, page 18-35. Springer, (2015)Benchmarking of communication techniques for GPUs.M. Bernaschi, M. Bisson, and D. Rossetti. J. Parallel Distrib. Comput., 73 (2): 250-255 (2013)Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips.A. Chagoya-Garzon, X. Guerin, F. Rousseau, F. Pétrot, D. Rossetti, A. Lonardo, P. Vicini, and P. Paolucci. IEEE International Workshop on Rapid System Prototyping, page 48-54. IEEE Computer Society, (2009)The Teraflop Parallel Computer APEmille.F. Aglietti, A. Bartolini, C. Battista, S. Cabasino, M. Cosimi, A. Michelotti, A. Monello, E. Panizzi, P. Paolucci, W. Rinaldi and 10 other author(s). HPCN Europe, volume 1225 of Lecture Notes in Computer Science, page 991-993. Springer, (1997)APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clustersR. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, A. Salamon, G. Salina, F. Simula and 2 other author(s). CoRR, (2011)Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, P. Paolucci, A. Lonardo, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)

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Disambiguation of "Rossetti, Davide"

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Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.

Please choose a person to relate this publication to

Davide Padeletti University of Stuttgart

PD Dr. rer. nat. Davide Cesare Veniani University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Rossetti, Davide"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.

Please choose a person to relate this publication to

Davide Padeletti University of Stuttgart

PD Dr. rer. nat. Davide Cesare Veniani University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
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Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.