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Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.

R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, P. Paolucci, A. Lonardo, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)

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Davide Padeletti University of Stuttgart

PD Dr. rer. nat. Davide Cesare Veniani University of Stuttgart

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Breadth First Search on APEnet+.M. Bernaschi, M. Bisson, E. Mastrostefano, and D. Rossetti. SC Companion, page 248-253. IEEE Computer Society, (2012)UCX: An Open Source Framework for HPC Network APIs and Beyond.P. Shamis, M. Venkata, M. Lopez, M. Baker, O. Hernandez, Y. Itigin, M. Dubman, G. Shainer, R. Graham, L. Liss and 10 other author(s). Hot Interconnects, page 40-43. IEEE Computer Society, (2015)Exploring OpenSHMEM Model to Program GPU-based Extreme-Scale Systems.S. Potluri, D. Rossetti, D. Becker, D. Poole, M. Venkata, O. Hernandez, P. Shamis, M. Lopez, M. Baker, and W. Poole. OpenSHMEM, volume 9397 of Lecture Notes in Computer Science, page 18-35. Springer, (2015)GPU peer-to-peer techniques applied to a cluster interconnect.R. Ammendola, M. Bernaschi, A. Biagioni, M. Bisson, M. Fatica, O. Frezza, F. Cicero, A. Lonardo, E. Mastrostefano, P. Paolucci and 4 other author(s). CoRR, (2013)NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features.A. Lonardo, F. Ameli, R. Ammendola, A. Biagioni, O. Frezza, G. Lamanna, F. Cicero, M. Martinelli, P. Paolucci, E. Pastorelli and 7 other author(s). CoRR, (2014)Benchmarking of communication techniques for GPUs.M. Bernaschi, M. Bisson, and D. Rossetti. J. Parallel Distrib. Comput., 73 (2): 250-255 (2013)Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips.A. Chagoya-Garzon, X. Guerin, F. Rousseau, F. Pétrot, D. Rossetti, A. Lonardo, P. Vicini, and P. Paolucci. IEEE International Workshop on Rapid System Prototyping, page 48-54. IEEE Computer Society, (2009)'Mutual Watch-dog Networking': Distributed Awareness of Faults and Critical Events in Petascale/Exascale systems.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report.R. Ammendola, A. Biagioni, O. Frezza, W. Geurts, G. Goossens, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula and 2 other author(s). CoRR, (2013)Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, P. Paolucci, A. Lonardo, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)

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Disambiguation of "Rossetti, Davide"

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Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.

Please choose a person to relate this publication to

Davide Padeletti University of Stuttgart

PD Dr. rer. nat. Davide Cesare Veniani University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Rossetti, Davide"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.

Please choose a person to relate this publication to

Davide Padeletti University of Stuttgart

PD Dr. rer. nat. Davide Cesare Veniani University of Stuttgart

Other publications of authors with the same name

Disambiguation

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Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.