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Disambiguation of "Casseau, Emmanuel"

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Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture.

, , , , , , and . DASIP, page 168-175. IEEE, (2010)

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Other publications of authors with the same name

Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems., , and . SoCC, page 175-178. IEEE, (2006)Automated multimode system design for high performance DSP applications., and . EUSIPCO, page 1289-1293. IEEE, (2009)Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design., , and . IEEE International Workshop on Rapid System Prototyping, page 240-243. IEEE Computer Society, (2005)On the FPGA-Based Implementation of a Flexible Waveform from a High-Level Description: Application to LTE FFT Case Study., , and . CrownCom, volume 172 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 545-557. Springer, (2016)Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses., , and . EUSIPCO, page 1-4. IEEE, (2005)C-based rapid prototyping for digital signal processing., , , , , and . EUSIPCO, page 1-4. IEEE, (2005)Exploiting reconfigurable SWP operators for multimedia applications., , , , , , and . ICASSP, page 1717-1720. IEEE, (2011)Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design., and . EURASIP J. Adv. Sig. Proc., (2011)Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis., , and . IEEE Trans. VLSI Syst., 16 (11): 1454-1464 (2008)Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs., , , , , and . Signal Processing Systems, 80 (1): 121-136 (2015)