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Disambiguation of "Dhillon, Yuvraj Singh"

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Low-power domino circuits using NMOS pull-up on off-critical paths.

, , , and . ASP-DAC, page 533-538. ACM Press, (2005)

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Arijit Singha Hazari University of Stuttgart

Prakhar Singhal University of Stuttgart

Shivendra Singh Parihar University of Stuttgart

Prabal Singh Verma University of Stuttgart

 

Other publications of authors with the same name

Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits., , , and . IOLTS, page 35-40. IEEE Computer Society, (2005)Low-power dual Vth pseudo dual Vdd domino circuits., , , and . SBCCI, page 273-277. ACM, (2004)Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages., , , and . VLSI Design, page 159-164. IEEE Computer Society, (2005)Sizing CMOS Circuits for Increased Transient Error Tolerance., , , and . IOLTS, page 11-16. IEEE Computer Society, (2004)Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level., , , and . ICCAD, page 693-700. IEEE Computer Society / ACM, (2003)Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits, , and . CoRR, (2007)Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance., , , and . VTS, page 298-303. IEEE Computer Society, (2005)Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits., , and . DATE, page 288-293. IEEE Computer Society, (2005)Low-power domino circuits using NMOS pull-up on off-critical paths., , , and . ASP-DAC, page 533-538. ACM Press, (2005)Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption., , and . J. Low Power Electronics, 3 (1): 78-95 (2007)