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Disambiguation of "Metra, Cecilia"

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Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits.

, , , and . IOLTS, page 35-40. IEEE Computer Society, (2005)

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Other publications of authors with the same name

Power Consumption of Fault Tolerant Busses., , , , and . IEEE Trans. VLSI Syst., 16 (5): 542-553 (2008)Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?., , and . IEEE Trans. Computers, 56 (3): 415-428 (2007)New ECC for Crosstalk Impact Minimization., , , and . IEEE Design & Test of Computers, 22 (4): 340-348 (2005)Online Testing Approach for Very Deep-Submicron ICs., and . IEEE Design & Test of Computers, 19 (2): 16-23 (2002)Error Correcting Codes for Crosstalk Effect Minimization., , and . DFT, page 257-. IEEE Computer Society, (2003)Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems., , , , and . IOLTS, page 135-140. IEEE Computer Society, (2004)Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST., , , , , and . IEEE Trans. Computers, 65 (8): 2484-2494 (2016)Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems., , , , and . DFT, page 233-240. IEEE Computer Society, (1998)Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks., , and . DFT, page 174-182. IEEE Computer Society, (1998)Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block., , , and . DFT, page 271-278. IEEE Computer Society, (1993)