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Disambiguation of "Abreu, Brunno"

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A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers

, , , , , , and . IEEE transactions on computers, 71 (2): 349-363 (2022)
DOI: 10.1109/TC.2021.3050978

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Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding., , , , , , , and . ICECS, page 490-493. IEEE, (2017)Exploiting absolute arithmetic for power-efficient sum of absolute differences., , , , , , and . ICECS, page 522-525. IEEE, (2017)Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors., , , , , , and . NEWCAS, page 309-312. IEEE, (2018)Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design., , , , , , and . IEEE Trans. on Circuits and Systems, 64-I (12): 3126-3137 (2017)Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation., , , , , , and . SBCCI, page 1-6. IEEE, (2018)Quality and Complexity Assessment of Learning-Based Image Compression Solutions., , , and . ICIP, page 599-603. IEEE, (2021)A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers, , , , , , and . IEEE transactions on computers, 71 (2): 349-363 (2022)HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators., , , , , and . MWSCAS, page 331-334. IEEE, (2019)The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures., , , , , , and . Circuits Syst. Signal Process., 41 (3): 1577-1595 (2022)Physical implementation of an ASIC-oriented SRAM-based viterbi decoder., , , , , , and . ICECS, page 526-529. IEEE, (2017)