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Disambiguation of "da Costa, Eduardo A. C."

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Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.

, , , , , , and . IEEE Trans. on Circuits and Systems, 64-I (12): 3126-3137 (2017)

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Vanessa Costalonga Martins University of Stuttgart

Francisco Costa Garcia University of Stuttgart

Maria Costa Jornet University of Stuttgart

A. Laukemann

A. Laukemann

 

Other publications of authors with the same name

Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths., , and . VLSI-SOC, page 307-. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization., , and . ICECS, page 352-355. IEEE, (2015)Power efficient 2-D rounded cosine transform with adder compressors for image compression., , , and . ICECS, page 348-351. IEEE, (2015)Energy-efficient Gaussian filter for image processing using approximate adder circuits., , , and . ICECS, page 450-453. IEEE, (2015)High performance Haar Wavelet transform architecture., , and . ECCTD, page 596-599. IEEE, (2011)SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder., , , and . ICECS, page 576-579. IEEE, (2015)Exploiting architectural solutions for IIR filter architecture with truncation error feedback., , , and . LASCAS, page 375-378. IEEE, (2016)High performance motion estimation architecture using efficient adder-compressors., , , , and . SBCCI, ACM, (2009)A Fixed-Point Natural Logarithm Approximation Hardware Design Using Taylor Series., , , and . NGCAS, page 53-56. IEEE, (2018)Maximal sharing of partial terms in MCM under minimal signed digit representation., , and . ECCTD, page 221-224. IEEE, (2005)