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Disambiguation of "Rocha, Leandro M. G."

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Physical implementation of an ASIC-oriented SRAM-based viterbi decoder.

, , , , , , and . ICECS, page 526-529. IEEE, (2017)

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Other publications of authors with the same name

Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation., , , , , , and . SBCCI, page 1-6. IEEE, (2018)Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors., , , , , , and . IET Comput. Digit. Tech., 15 (3): 230-240 (2021)A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers, , , , , , and . IEEE transactions on computers, 71 (2): 349-363 (2022)Physical implementation of an ASIC-oriented SRAM-based viterbi decoder., , , , , , and . ICECS, page 526-529. IEEE, (2017)A power-predictive environment for fast and power-aware ASIC-based FIR filter design., , , , , and . SBCCI, page 168-173. ACM, (2017)Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors., , , , , , and . NEWCAS, page 309-312. IEEE, (2018)Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers., , , , and . ICECS, page 478-481. IEEE, (2017)Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing., , , , , , , , and . ISCAS, page 1-5. IEEE, (2019)