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Disambiguation of "da Costa, Eduardo Antônio César"

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The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures.

, , , , , , and . Circuits Syst. Signal Process., 41 (3): 1577-1595 (2022)

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César Cardona Marin University of Stuttgart

Antonio Raiolo University of Stuttgart

Vanessa Costalonga Martins University of Stuttgart

Francisco Costa Garcia University of Stuttgart

Maria Costa Jornet University of Stuttgart

 

Other publications of authors with the same name

The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures., , , , , , and . Circuits Syst. Signal Process., 41 (3): 1577-1595 (2022)A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers, , , , , , and . IEEE transactions on computers, 71 (2): 349-363 (2022)Bridging the Gap Between Voltage Over-Scaling and Joint Hardware Accelerator-Algorithm Closed-Loop, , , , and . IEEE transactions on circuits and systems for video technology, 32 (1): 398-410 (2022)On the Resiliency of NCFET Circuits Against Voltage Over-Scaling, , , , , , , and . IEEE transactions on circuits and systems. 1, Regular papers, 68 (4): 1481-1492 (2021)Power System Frequency Estimation U Sing the Kernel Least Mean Square Algorithm and the Clarke Transform., , and . NGCAS, page 134-137. IEEE, (2018)Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators., , , , and . IEEE Trans. on Circuits and Systems, 66-I (6): 2137-2150 (2019)Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers., , , , , and . IEEE Trans. on Circuits and Systems, 66-I (2): 680-693 (2019)A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding., , , and . SBCCI, page 1-6. IEEE, (2016)