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Power efficient branch prediction through early identification of branch addresses.

, and . CASES, page 169-178. ACM, (2006)

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Aggressive Test Power Reduction Through Test Stimuli Transformation., and . ICCD, page 542-547. IEEE Computer Society, (2003)Mobile ecosystem driven application-specific low-power control microarchitecture., and . ICCD, page 720-727. IEEE Computer Society, (2015)Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs.. ICCD, page 112-117. IEEE Computer Society, (1996)Scan Power Reduction Through Test Data Transition Frequency Analysis., , and . ITC, page 844-850. IEEE Computer Society, (2002)Autonomous Yet Deterministic Test of SOC Cores., and . ITC, page 1359-1368. IEEE Computer Society, (2004)Optimal Self-Recovering Microarchitecture Synthesis., and . FTCS, page 512-521. IEEE Computer Society, (1993)Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection., and . IEEE Trans. VLSI Syst., 20 (12): 2170-2183 (2012)The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations., and . IEEE Trans. Computers, 54 (1): 61-75 (2005)Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs., and . IEEE Trans. Computers, 52 (11): 1480-1489 (2003)Automatic Synthesis of Self-Recovering VLSI Systems., and . IEEE Trans. Computers, 45 (2): 131-142 (1996)