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Disambiguation of "Jha, Niraj K."

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High-level macro-modeling and estimation techniques for switching activity and power consumption.

, , and . IEEE Trans. VLSI Syst., 11 (4): 538-557 (2003)

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Dr. Abhinav Jha University of Stuttgart

K. Stahl

K. Gaiser

K. Lindow

Grzegorz K. Karch

 

Other publications of authors with the same name

Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs., and . IEEE Trans. Parallel Distrib. Syst., 4 (8): 864-874 (1993)Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip., and . IJES, 1 (1/2): 2-13 (2005)Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks., , and . HPCA, page 91-102. IEEE Computer Society, (2003)High-level Synthesis of Multi-process Behavioral Descriptions., , , and . VLSI Design, page 467-473. IEEE Computer Society, (2003)Task Graph Extraction for Embedded System Synthesis., and . VLSI Design, page 480-. IEEE Computer Society, (2003)Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems., and . VLSI Design, page 719-. IEEE Computer Society, (2002)Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip., and . VLSI Design, page 274-281. IEEE Computer Society, (2002)Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability., , and . VLSI Design, page 171-176. IEEE Computer Society, (1995)Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (7): 1339-1345 (2007)SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (3): 508-526 (2007)