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Disambiguation of "Lingappan, Loganathan"

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Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits.

, and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (7): 1339-1345 (2007)

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Other publications of authors with the same name

Hardware-in-the-loop model-less diagnostic test generation., , and . HLDVT, page 128-135. IEEE, (2016)A Novel SMT-Based Technique for LFSR Reseeding., , , and . VLSI Design, page 394-399. IEEE Computer Society, (2012)Information-theoretic and statistical methods of failure log selection for improved diagnosis., , , and . ITC, page 1-10. IEEE, (2015)Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs., , and . Asian Test Symposium, page 59-64. IEEE Computer Society, (2010)A SMT-based diagnostic test generation method for combinational circuits., , , and . VTS, page 215-220. IEEE Computer Society, (2012)Online Scan Diagnosis : A Novel Approach to Volume Diagnosis., , , and . ITC, page 1-10. IEEE, (2018)A Test Generation Framework for Quantum Cellular Automata Circuits., , and . IEEE Trans. VLSI Syst., 15 (1): 24-36 (2007)Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (7): 1339-1345 (2007)Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (10): 2193-2206 (2006)Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip., , , , and . VLSI Design, page 65-70. IEEE Computer Society, (2005)