%0 Journal Article %1 journals/tcad/LingappanJ07 %A Lingappan, Loganathan %A Jha, Niraj K. %D 2007 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 7 %P 1339-1345 %T Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. %U http://dblp.uni-trier.de/db/journals/tcad/tcad26.html#LingappanJ07 %V 26

@article{journals/tcad/LingappanJ07, added-at = {2008-04-08T00:00:00.000+0200}, author = {Lingappan, Loganathan and Jha, Niraj K.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/28a3ebbbd3d71b635d01eb29cf9162583/dblp}, ee = {http://dx.doi.org/10.1109/TCAD.2006.888268}, interhash = {e61b5673701a8cf359022f642993a437}, intrahash = {8a3ebbbd3d71b635d01eb29cf9162583}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 7, pages = {1339-1345}, timestamp = {2016-02-02T10:07:59.000+0100}, title = {Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad26.html#LingappanJ07}, volume = 26, year = 2007 }