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A Unified Design Space for Regular Parallel Prefix Adders., and . DATE, page 1386-1387. IEEE Computer Society, (2004)Large-signal two-terminal device model for nanoelectronic circuit analysis., , and . IEEE Trans. VLSI Syst., 12 (11): 1201-1208 (2004)The POWER8TM processor: Designed for big data, analytics, and cloud environments., , , , , , , , , and 10 other author(s). ICICDT, page 1-4. IEEE, (2014)Bridging high performance and low power in processor design., , , and . ISLPED, page 183-188. ACM, (2014)Research From the IEEE IBM AI Compute and Emerging Technology Symposia., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (3): 435-438 (2019)A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)., , , , , , , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 307-316. Springer, (2009)Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction., , , , , , , , , and 2 other author(s). IEEE Trans. VLSI Syst., 23 (3): 534-543 (2015)14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation., , , , and . VLSIC, page 268-. IEEE, (2015)The CMOS/nano interface from a circuits perspective., and . ISCAS (4), page 904-907. IEEE, (2003)Multi-Dimensional Circuit and Micro-Architecture Level Optimization., , , , and . ISQED, page 275-280. IEEE Computer Society, (2007)