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A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).

, , , , , , , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 307-316. Springer, (2009)

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Clocking and clocked storage elements in a multi-gigahertz environment.. IBM Journal of Research and Development, 47 (5-6): 567-584 (2003)Introduction., and . VLSI Signal Processing, 3 (4): 263 (1991)Design Strategies for Optimal Multiplier Circuits., , , and . IEEE Symposium on Computer Arithmetic, page 42-49. IEEE Computer Society, (1995)Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders., , and . ARITH, page 10-17. IEEE, (2015)Dynamic Flip-Flop with Improved Power., and . ICCD, page 323-326. IEEE Computer Society, (2000)An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis.. IEEE Trans. VLSI Syst., 2 (1): 124-128 (1994)Dual-edge triggered storage elements and clocking strategy for low-power systems., and . IEEE Trans. VLSI Syst., 13 (5): 577-590 (2005)Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations., , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 360-369. Springer, (2006)Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations., and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 127-136. Springer, (2006)Computing at the ultimate low-energy limits.. SBCCI, page 1. ACM, (2010)