PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Bahukudumbi, Sudarshan"

Author of the publication

copydeleteadd this publication to your clipboard
Wafer-Level Modular Testing of Core-Based SoCs.

, and . IEEE Trans. VLSI Syst., 15 (10): 1144-1154 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Bahukudumbi, Sudarshan
add a person with the name Bahukudumbi, Sudarshan
 

Other publications of authors with the same name

Power Management for Wafer-Level Test During Burn-In., and . ATS, page 231-236. IEEE Computer Society, (2008)Power-aware SoC test planning for effective utilization of port-scalable testers., , and . ACM Trans. Design Autom. Electr. Syst., 13 (3): 53:1-53:19 (2008)A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores., and . VLSI Design, page 804-807. IEEE Computer Society, (2005)Wafer-Level Modular Testing of Core-Based SoCs., and . IEEE Trans. VLSI Syst., 15 (10): 1144-1154 (2007)Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs., , , and . IEEE Trans. VLSI Syst., 17 (4): 587-592 (2009)Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (1): 111-120 (2009)Test-Pattern Ordering for Wafer-Level Test-During-Burn-In., and . VTS, page 193-198. IEEE Computer Society, (2008)AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs., , , and . ASP-DAC, page 823-828. IEEE Computer Society, (2007)Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs., and . ITC, page 1-10. IEEE Computer Society, (2006)Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In., and . IEEE Trans. VLSI Syst., 17 (12): 1730-1741 (2009)