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Disambiguation of "Bahukudumbi, Sudarshan"

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A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores.

, and . VLSI Design, page 804-807. IEEE Computer Society, (2005)

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Other publications of authors with the same name

Power Management for Wafer-Level Test During Burn-In., and . ATS, page 231-236. IEEE Computer Society, (2008)A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores., and . VLSI Design, page 804-807. IEEE Computer Society, (2005)Power-aware SoC test planning for effective utilization of port-scalable testers., , and . ACM Trans. Design Autom. Electr. Syst., 13 (3): 53:1-53:19 (2008)Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (1): 111-120 (2009)Wafer-Level Modular Testing of Core-Based SoCs., and . IEEE Trans. VLSI Syst., 15 (10): 1144-1154 (2007)Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs., , , and . IEEE Trans. VLSI Syst., 17 (4): 587-592 (2009)Test-Pattern Ordering for Wafer-Level Test-During-Burn-In., and . VTS, page 193-198. IEEE Computer Society, (2008)Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs., and . ITC, page 1-10. IEEE Computer Society, (2006)AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs., , , and . ASP-DAC, page 823-828. IEEE Computer Society, (2007)Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs., , and . DATE, page 1103-1106. ACM, (2008)