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AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.

, , , and . ASP-DAC, page 823-828. IEEE Computer Society, (2007)

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Statistical Test Development for Analog Circuits Under High Process Variations., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (8): 1465-1477 (2007)An analytical technique for characterization of transceiver IQ imbalances in the loop-back mode., and . DATE, page 1084-1089. IEEE, (2012)Approximating the age of RF/analog circuits through re-characterization and statistical estimation., , , and . DATE, page 1-4. European Design and Automation Association, (2014)Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis., and . VTS, page 213-222. IEEE Computer Society, (2002)Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems., and . VTS, page 149-156. IEEE Computer Society, (2000)Parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitions., and . ICCAD, page 73-79. IEEE Computer Society, (2005)Testing of Droplet-Based Microelectrofluidic Systems., , and . ITC, page 1192-1200. IEEE Computer Society, (2003)Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits., and . ICCD, page 161-170. IEEE Computer Society, (2005)Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits., and . ICCD, page 258-264. IEEE Computer Society, (2002)Analysis and Mitigation of Electromigration in RF Circuits: An LNA Case Study., , and . European Test Symposium, page 215. IEEE Computer Society, (2011)