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A Hardware Virtual Machine for the Networked Reconfiguration., , , , , , and . IEEE International Workshop on Rapid System Prototyping, page 194-199. IEEE Computer Society, (2000)System Level Architecture Exploration for Reconfigurable Systems On Chip., , , , , , and . FPL, page 1-6. IEEE, (2006)Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java., , , , , , and . SCOPES, volume 2826 of Lecture Notes in Computer Science, page 313-328. Springer, (2003)Towards high performance sub-10nm finW bulk FinFET technology., , , , , , , , , and 10 other author(s). ESSDERC, page 131-134. IEEE, (2016)A Programming Environment for the Design of Complex High Speed ASICs., , , , and . DAC, page 315-320. ACM Press, (1998)Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications., , , , and . ED&TC, page 542-546. IEEE Computer Society, (1997)A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement., , , , and . DATE, page 271-. IEEE Computer Society / ACM, (1999)REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures., , , , and . DAC, page 694-697. ACM Press, (1989)Timing optimization by bit-level arithmetic transformations., , , and . EURO-DAC, page 48-53. IEEE Computer Society, (1995)