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Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE Profile., , and . DSD, page 251-254. IEEE Computer Society, (2010)Automatic workload generation for system-level exploration based on modified GCC compiler., , and . DATE, page 369-374. IEEE, (2010)System Level Performance Simulation of Distributed GENESYS Applications on Multi-core Platforms., , , and . DASC, page 313-320. IEEE Computer Society, (2011)Multi-threading support for system-level performance simulation of multi-core architectures., , , and . ARCS Workshops, VDE-Verlag, (2011)Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models., , and . EUROMICRO, page 172-181. IEEE Computer Society, (1997)A Network on Chip Architecture and Design Methodology., , , , , , , and . ISVLSI, page 117-124. IEEE Computer Society, (2002)Linking GENESYS application architecture modelling with platform performance simulation., , , , and . FDL, page 1-6. IEEE, (2009)Combining UML2 Application and SystemC Platform Modelling for Performance Evaluation of Real-Time Embedded Systems., , , , , , and . EURASIP J. Emb. Sys., (2008)Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach., , , , , , , , , and 11 other author(s). ISVLSI, page 518-523. IEEE Computer Society, (2010)System-Level Modeling of Dynamically Reconfigurable Co-processors., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 881-885. Springer, (2004)