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Disambiguation of "Lu, Zhonghai"

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Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach.

, , , , , , , , , , , , , , , , , , , , and . ISVLSI, page 518-523. IEEE Computer Society, (2010)

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Hao Lu University of Stuttgart

Yong Lu University of Stuttgart

Junqi Lu University of Stuttgart

Lu Chen University of Stuttgart

Fiona Dominique Lüdecke University of Stuttgart

 

Other publications of authors with the same name

Admitting and ejecting flits in wormhole-switched networks on chip., and . IET Computers & Digital Techniques, 1 (5): 546-556 (2007)A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip., , , , , and . ISVLSI, page 19-24. IEEE Computer Society, (2011)Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing., , , and . ISVLSI, page 80-85. IEEE Computer Society, (2010)Analysis and evaluation of per-flow delay bound for multiplexing models., , and . DATE, page 1-4. European Design and Automation Association, (2014)Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling., , and . DATE, page 538-541. IEEE, (2012)Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip., , and . DDECS, page 92-97. IEEE Computer Society, (2008)Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics., , , , , , and . FPT, page 177-183. IEEE, (2007)Thread Voting DVFS for Manycore NoCs., and . IEEE Trans. Computers, 67 (10): 1506-1524 (2018)Analyzing Credit-Based Router-to-Router Flow Control for On-Chip Networks., , , and . IEICE Transactions, 92-C (10): 1276-1283 (2009)Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (6): 986-999 (2015)