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System Level Architecture Exploration for Reconfigurable Systems On Chip.

K. Masselos, K. Tiensyrjä, Y. Qu, N. Voros, M. Cupák, L. Rijnders, and M. Pettissalo. FPL, page 1-6. IEEE, (2006)

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Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Dr. Moritz Quaas University of Stuttgart

Other publications of authors with the same name

Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices.Y. Qu, J. Soininen, and J. Nurmi. DATE, page 147-152. EDA Consortium, San Jose, CA, USA, (2007)Modeling and Inference of Extended Interval Temporal Logic for Nondeterministic Intervals.C. Lin, Z. Shan, T. Liu, Y. Qu, and F. Ren. IEEE Trans. Systems, Man, and Cybernetics, Part A, 35 (5): 682-696 (2005)Application - Platform Performance Modeling and Evaluation.J. Kreku, M. Hoppari, T. Kestilä, Y. Qu, J. Soininen, and K. Tiensyrjä. FDL, page 43-48. IEEE, (2008)Layered UML Workload and SystemC Platform Models.J. Kreku, Y. Qu, J. Soininen, and K. Tiensyrjä. FDL, page 223-229. ECSI, (2006)A Genetic Algorithm for Scheduling Tasks onto Dynamically Reconfigurable Hardware.Y. Qu, J. Soininen, and J. Nurmi. ISCAS, page 161-164. IEEE, (2007)A Game-Based Intrusion Tolerant Mechanism for Grid Service.Y. Wang, C. Lin, Y. Yang, J. Lv, and Y. Qu. GCC, page 380-386. IEEE Computer Society, (2006)Grid Service Workflow Models and Their Equivalent Simplification Methods.Y. Wang, C. Lin, Y. Yang, and Y. Qu. GCC Workshops, page 302-307. IEEE Computer Society, (2006)An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications.Y. Qu, J. Soininen, and J. Nurmi. FPL, page 648-653. IEEE, (2005)System Level Architecture Exploration for Reconfigurable Systems On Chip.K. Masselos, K. Tiensyrjä, Y. Qu, N. Voros, M. Cupák, L. Rijnders, and M. Pettissalo. FPL, page 1-6. IEEE, (2006)RF Steganography via LFM Chirp Radar Signals.Z. Zhang, Y. Qu, Z. Wu, M. Nowak, J. Ellinger, and M. Wicks. IEEE Trans. Aerospace and Electronic Systems, 54 (3): 1221-1236 (2018)

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Disambiguation of "Qu, Yang"

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URL
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System Level Architecture Exploration for Reconfigurable Systems On Chip.

Please choose a person to relate this publication to

Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Dr. Moritz Quaas University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Qu, Yang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML System Level Architecture Exploration for Reconfigurable Systems On Chip.

Please choose a person to relate this publication to

Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Dr. Moritz Quaas University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

System Level Architecture Exploration for Reconfigurable Systems On Chip.