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Disambiguation of "Borkar, Shekhar Y."

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Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS.

, , , , , , , , and . CICC, page 1-4. IEEE, (2014)

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Gül Yalman University of Stuttgart

Seda Yilmaz University of Stuttgart

Judith Yacar-Boitier University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Peihan Yang University of Stuttgart

 

Other publications of authors with the same name

A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 41 (1): 256-264 (2006)Microarchitecture and Design Challenges for Gigascale Integration.. MICRO, page 3. IEEE Computer Society, (2004)Future of interconnect fabric: a contrarian view.. SLIP, page 1-2. ACM, (2010)Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections., , , and . Low Power Networks-on-Chip, Springer, (2011)Want to be a bug buster?. Commun. ACM, 53 (2): 105 (2010)Is statistical timing statistically significant?, , , , , , , and . DAC, page 498. ACM, (2004)An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS., , , , and . ISLPED, page 103-106. ACM, (2005)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)Circuit techniques for dynamic variation tolerance., , , , , , and . DAC, page 4-7. ACM, (2009)Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2014)