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VHDL fault simulation for defect-oriented test and diagnosis of digital ICs.

J. Teixeira, F. Celeiro, L. Dias, J. Ferreira, and M. Santos. EURO-DAC, page 450-455. IEEE Computer Society Press, (1996)

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Joao Augusto Sobral da Silva University of Stuttgart

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On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.M. Santos, I. Teixeira, J. Teixeira, S. Manich, L. Balado, and J. Figueras. J. Electronic Testing, 20 (4): 345-355 (2004)RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage.M. Santos, F. Gonçalves, I. Teixeira, and J. Teixeira. J. Electronic Testing, 18 (2): 179-187 (2002)On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits.A. Casimiro, F. Gonçalves, J. Teixeira, and M. Santos. DFT, page 263-270. IEEE Computer Society, (1994)MOSYS A Methodology for Automatic Object Identification from System Specification.L. Becker, C. Pereira, O. Dias, I. Teixeira, and J. Teixeira. ISORC, page 198-201. IEEE Computer Society, (2000)Fault Modeling and Defect Level Projections in Digital ICs.J. de Sousa, F. Gonçalves, J. Teixeira, and T. Williams. EDAC-ETC-EUROASIC, page 436-442. IEEE Computer Society, (1994)Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits.J. Semião, J. Rodríguez-Andina, F. Vargas, M. Santos, I. Teixeira, and J. Teixeira. DDECS, page 34-37. IEEE Computer Society, (2008)Aging-Aware Power or Frequency Tuning With Predictive Fault Detection.J. Pachito, C. Martins, B. Jacinto, J. Semião, J. Vázquez, V. Champac, M. Santos, I. Teixeira, and J. Teixeira. IEEE Design & Test of Computers, 29 (5): 27-36 (2012)Automatic Configuration of a Medical Imaging System to Unknown Delays in Synchronous Input Data Channels.C. Leong, J. Teixeira, I. Teixeira, R. Bugalho, M. Ferreira, P. Rodrigues, J. Silva, P. Lousã, and J. Varela. ISCAS, page 1185-1188. IEEE, (2010)Low Power BIST by Filtering Non-Detecting Vectors.S. Manich, A. Gabarró, M. Lopez, J. Figueras, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Teixeira, and M. Santos. J. Electronic Testing, 16 (3): 193-202 (2000)Investigating the Use of BICS to detect resistive-open defects in SRAMs.R. Chipana, L. Bolzani, F. Vargas, J. Semião, J. Rodríguez-Andina, I. Teixeira, and J. Teixeira. IOLTS, page 200-201. IEEE Computer Society, (2010)

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Disambiguation of "Teixeira, João Paulo"

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VHDL fault simulation for defect-oriented test and diagnosis of digital ICs.

Please choose a person to relate this publication to

Joao Augusto Sobral da Silva University of Stuttgart

Other publications of authors with the same name

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PUMA

Disambiguation of "Teixeira, João Paulo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML VHDL fault simulation for defect-oriented test and diagnosis of digital ICs.

Please choose a person to relate this publication to

Joao Augusto Sobral da Silva University of Stuttgart

Other publications of authors with the same name

Disambiguation

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VHDL fault simulation for defect-oriented test and diagnosis of digital ICs.