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Disambiguation of "Gonçalves, Fernando M."

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RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage.

, , , and . J. Electronic Testing, 18 (2): 179-187 (2002)

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M. Nudischer

M. Kratzer

M. Liewald

M. Fittingho

M. Christmann

 

Other publications of authors with the same name

A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits., , and . FPL, page 481-486. IEEE, (2005)RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage., , , and . J. Electronic Testing, 18 (2): 179-187 (2002)Hardware/software specialization through aspects: The LARA approach., , , , , and . ICSAMOS, page 260-267. IEEE, (2012)Fault Modeling and Defect Level Projections in Digital ICs., , , and . EDAC-ETC-EUROASIC, page 436-442. IEEE Computer Society, (1994)On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits., , , and . DFT, page 263-270. IEEE Computer Society, (1994)RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems., , , and . J. Electronic Testing, 17 (3-4): 311-319 (2001)Defect-oriented test quality assessment using fault sampling and simulation., , , and . ITC, page 35-42. IEEE Computer Society, (1998)On-Detector Electronics of the Clear PEM Scanner., , , , , , , , , and 15 other author(s). BIODEVICES, page 355-358. INSTICC Press, (2009)Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level., , , and . ITC, page 377-385. IEEE Computer Society, (2001)Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique., , , and . VTS, page 326-332. IEEE Computer Society, (1999)