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Disambiguation of "Manich, Salvador"

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On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.

, , , , , and . J. Electronic Testing, 20 (4): 345-355 (2004)

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Other publications of authors with the same name

Differential scan-path: A novel solution for secure design-for-testability., , , and . ITC, page 1-9. IEEE Computer Society, (2013)Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring., , and . VTS, page 124-129. IEEE Computer Society, (1996)Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 80-89. Springer, (2003)Improving security in cache memory by power efficient scrambling technique., , and . IET Computers & Digital Techniques, 9 (6): 283-292 (2015)Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model., and . ED&TC, page 597-602. IEEE Computer Society, (1997)Fault-Secure Parity Prediction Arithmetic Operators., , , and . IEEE Design & Test of Computers, 14 (2): 60-71 (1997)A Highly Time Sensitive XOR Gate for Probe Attempt Detectors., and . IEEE Trans. on Circuits and Systems, 60-II (11): 786-790 (2013)Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity., , , , , , , and . ISCAS (1), page 110-113. IEEE, (1999)Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations., , and . ED&TC, page 186-194. IEEE Computer Society, (1996)RRAM based cell for hardware security applications., , and . IVSW, page 1-6. IEEE, (2016)