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Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs., , , , and . DFT, page 109-116. IEEE Computer Society, (1993)Performance sensor for tolerance and predictive detection of delay-faults., , , , , , and . DFT, page 110-115. IEEE Computer Society, (2014)Enhancing the Tolerance to Power-Supply Instability in Digital Circuits., , , , , , and . ISVLSI, page 207-212. IEEE Computer Society, (2007)Quality of Electronic Design: From Architectural Level to Test Coverage., , , , and . ISQED, page 197-. IEEE Computer Society, (2000)Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits., , , , , , and . DDECS, page 295-300. IEEE Computer Society, (2007)Gate Driver Voltage Optimization for Multi-Mode Low Power DC-DC Conversion., , , , and . J. Low Power Electronics, 5 (2): 241-254 (2009)Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System., , , and . J. Electronic Testing, 18 (3): 285-294 (2002)Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro., , , and . IOLTW, page 197-201. IEEE Computer Society, (2001)Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies., , , , , , and . IOLTS, page 223-228. IEEE Computer Society, (2009)Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits., , , , , , and . IOLTS, page 227-232. IEEE Computer Society, (2008)