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Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder.

, , , , and . ISVLSI, page 445-446. IEEE Computer Society, (2007)

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Embedded Systems Design with Frontend Compilers., , , and . ICCD, page 200-205. IEEE Computer Society, (1996)A Statistical Sampler for a New On-line Analog Test Method., , and . IOLTW, page 79-. IEEE Computer Society, (2002)Gradient pile up for edge detection on hardware., , , and . ISCAS (6), page 5834-5837. IEEE, (2005)HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV., , , and . ISCAS, page 25-28. IEEE, (2008)Automatic generation of neural networks for image processing., , and . ISCAS, IEEE, (2006)NoC Power Optimization Using a Reconfigurable Router., , , , , and . ISVLSI, page 235-240. IEEE Computer Society, (2009)Memory subsystem architecture design for multimedia applications., and . ISVLSI, page 213-214. IEEE Computer Socity, (2013)Gossip NoC - Avoiding Timing Side-Channel Attacks through Traffic Management., , , and . ISVLSI, page 601-606. IEEE Computer Society, (2016)A Framework for Automatic Recognition of Cell Damage on Microscopic Images using Artificial Neural Networks., , , , , and . EMBC, page 636-639. IEEE, (2018)Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform., , , , , and . ARC, volume 3985 of Lecture Notes in Computer Science, page 134-145. Springer, (2006)