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Reconfigurable communications for image processing applications., , and . IPDPS, IEEE, (2006)A Contextual Resources use: a Proof of Concept through the APACHES' Platform., , , , and . DDECS, page 44-49. IEEE Computer Society, (2006)Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues., , and . Int. J. Reconfig. Comp., (2013)Towards an Efficient Memory Architecture for Video Decoding Systems., , , and . SBESC, page 198-203. IEEE Computer Society, (2012)Gradient Pile up Algorithm for Edge Enhancement and Detection., , , and . ICIAR (1), volume 3212 of Lecture Notes in Computer Science, page 187-194. Springer, (2004)Adaptive Shared Memory Control for Multimedia Systems-on-Chip., , , , and . SBCCI, page 46:1-46:7. ACM, (2014)Gradient pile up for edge detection on hardware., , , and . ISCAS (6), page 5834-5837. IEEE, (2005)Automatic generation of neural networks for image processing., , and . ISCAS, IEEE, (2006)A new march sequence to fit DDR SDRAM test in burst mode., , and . SBCCI, page 28-33. ACM, (2008)Integration issues on the development of an h.264/AVC video decoder SoC for SBTVD set top box., , and . SBCCI, page 125-130. ACM, (2011)