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LUT-based FPGA technology mapping under arbitrary net-delay models., , , and . Computers & Graphics, 18 (4): 507-516 (1994)LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization., , , and . IEEE Trans. VLSI Syst., 18 (4): 564-577 (2010)Synthesis Algorithm for Application-Specific Homogeneous Processor Networks., , , and . IEEE Trans. VLSI Syst., 17 (9): 1318-1329 (2009)Compilation and architecture support for customized vector instruction extension., , , , , , , and . ASP-DAC, page 652-657. IEEE, (2012)A Fully Pipelined and Dynamically Composable Architecture of CGRA., , , , and . FCCM, page 9-16. IEEE Computer Society, (2014)Coordinated resource optimization in behavioral synthesis., , and . DATE, page 1267-1272. IEEE, (2010)Incremental CAD., , , and . ICCAD, page 236-243. IEEE Computer Society, (2000)Thermal via planning for 3-D ICs., and . ICCAD, page 745-752. IEEE Computer Society, (2005)Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design., , , , , , and . DATE, page 45-50. IEEE, (2012)A new algorithm for standard cell global routing., and . Integration, 14 (1): 49-65 (1992)