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A Fully Pipelined and Dynamically Composable Architecture of CGRA.

, , , , and . FCCM, page 9-16. IEEE Computer Society, (2014)

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Incremental CAD., , , and . ICCAD, page 236-243. IEEE Computer Society, (2000)Thermal via planning for 3-D ICs., and . ICCAD, page 745-752. IEEE Computer Society, (2005)Compilation and architecture support for customized vector instruction extension., , , , , , , and . ASP-DAC, page 652-657. IEEE, (2012)Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design., , , , , , and . DATE, page 45-50. IEEE, (2012)Coordinated resource optimization in behavioral synthesis., , and . DATE, page 1267-1272. IEEE, (2010)LUT-based FPGA technology mapping under arbitrary net-delay models., , , and . Computers & Graphics, 18 (4): 507-516 (1994)Domain-specific processor with 3D integration for medical image processing., , , , , and . ASAP, page 247-250. IEEE Computer Society, (2011)Energy-efficient computing using adaptive table lookup based on nonvolatile memories., , , , and . ISLPED, page 280-285. IEEE, (2013)Buffer block planning for interconnect planning and prediction., , and . IEEE Trans. VLSI Syst., 9 (6): 929-937 (2001)Pin assignment with global routing for general cell designs.. IEEE Trans. on CAD of Integrated Circuits and Systems, 10 (11): 1401-1412 (1991)